PCB Stackup and Impedance Control: A Practical Introduction

A stackup is the ordered list of copper layers and insulating layers that make up a finished board, with the thickness and material of each. Core is a rigid, pre-cured dielectric with copper already bonded to both sides. Prepreg is glass cloth pre-impregnated with partially cured resin, which flows and bonds the layers together during lamination.

The stackup defines the finished board thickness and, just as important, the distance between each signal layer and its nearest reference plane. Those distances control impedance, coupling and how closely power and ground planes couple to each other. Because core and prepreg thicknesses come in discrete values, the final numbers come from combinations the fabricator actually stocks.

Routing density is the first pressure to add layers. Dense BGAs and large net counts need extra signal layers to escape and route, and layer counts are almost always even because boards are built from core pairs.

The second pressure is return paths and EMI. A signal layer next to a solid, uninterrupted reference plane gives its return current a clear path directly beneath the trace, which reduces loop area, crosstalk and both radiated and received interference. Pairing each signal layer with an adjacent plane is often the main reason four, six or more layers are chosen.

More layers cost more, so the right count balances routing, signal integrity and budget rather than aiming for the smallest or largest number. A well-planned four-layer board can outperform a poorly planned six-layer one.

Controlled impedance means a trace is built so that its characteristic impedance stays close to a target value along its length, so fast edges are not partly reflected wherever the impedance changes. It matters when signal rise times are short relative to the trace length, which is why it appears on high-speed interfaces, RF lines and some fast memory and serial links. Slow signals on short traces usually do not need it.

Impedance can be specified single-ended, for one trace against its reference plane, or differential, for a coupled pair carrying opposite signals. Differential impedance also depends on the spacing between the two traces, in addition to the factors that apply to each trace alone.

Four things set the result: trace width, the thickness of the dielectric between the trace and its reference plane, the dielectric constant of that material, and copper thickness, which has a smaller effect. Wider traces lower impedance, thicker dielectric raises it, and a higher dielectric constant lowers it. Your layout tool's field solver computes the numbers, and the fabricator confirms them against its own process data.

Microstrip traces run on an outer layer with a reference plane on one side and air or solder mask on the other. Stripline traces run on an inner layer between two reference planes. The choice is usually driven by where a signal must be routed and what the stackup offers.

Fabricators build from the materials and press cycles they stock, so the stackup you assume in your CAD tool may not be buildable as drawn. Dielectric thickness shifts after lamination as resin flows, and plating changes the thickness of outer-layer copper. Agreeing a stackup early means your impedance calculations start from the real construction.

Ask the fabricator to propose a stackup for your layer count, thickness and impedance targets, and review it before routing. Then list the controlled nets, their layers, target impedances and tolerances in the fabrication notes. Because the fabricator may adjust trace widths slightly to hit the targets, confirm what compensation they apply.

Ask for an impedance report with each build. Fabricators typically add test coupons to the panel, measure them, commonly with time-domain reflectometry, and report the results against target. A coupon samples the panel rather than your exact traces, but a result within tolerance is good evidence that the process hit its mark.

High-frequency return current takes the path of least impedance, which is usually directly beneath the signal trace on the adjacent reference plane. If that plane is interrupted by a slot, a split or a dense row of clearance holes, the return must detour. The loop area grows, crosstalk and radiation rise, and the trace impedance changes where its reference is disturbed.

The classic mistake is routing a fast signal across a split between two plane regions. Keep fast signals over continuous plane, and where a signal changes layers and its reference plane changes with it, place a stitching via nearby so the return current can follow.

Standard FR-4 is a glass-reinforced epoxy laminate that is widely available, well understood and inexpensive, and it serves a large share of designs, including many fast digital interfaces. Its dielectric constant and loss vary with frequency and between products, and the glass weave can cause local variation in impedance and timing on very fast pairs.

Low-loss and high-speed laminates offer lower dissipation, steadier electrical properties across frequency and often tighter control of dielectric constant. The price is higher material cost and sometimes less common processing and longer lead times. They tend to pay off when channels are long, data rates are high or loss budgets are tight, and rarely on short, moderate-speed boards.

This is a trade-off, not a rule. Estimate the loss budget for your longest channel, compare it with what FR-4 can deliver, and discuss options with the fabricator, including hybrid stackups that use premium material only on critical layers. Also check the temperature rating against your assembly process and confirm material availability before committing.

High-density interconnect (HDI) uses laser-drilled microvias, finer lines and often sequential lamination to route more in less area. Microvias are small, shallow holes spanning one or two layers, which is why they suit fine-pitch BGAs where mechanical drills and through vias cannot escape every pin.

Consider HDI when pitch is too tight to escape with through vias, when board area is constrained, or when the stubs left by long through-hole vias would hurt very fast signals. HDI raises cost and lead time, and each extra lamination cycle adds risk, so use the simplest structure that solves the problem.

Involve the fabricator before layout to confirm which structures, such as stacked or staggered microvias, and which aspect-ratio limits they support. IPC-2221 and IPC-2222 are common references for general rigid-board design rules.