Schematic Review Checklist: 12 Checks Before PCB Layout

A schematic error costs a few minutes to fix on screen and a board spin to fix after fabrication. Layout also locks in decisions that are expensive to unwind, so the schematic is the cheapest place to find mistakes.

The most useful review is a structured one, done by someone other than the author and worked against datasheets rather than memory. The twelve checks below are ordered roughly by how often they cause a dead or misbehaving first prototype.

Start by drawing the power tree: every source, regulator and load, with the expected voltage and current at each node. Add up the worst-case load on each rail and compare it with the rated output of the regulator, including startup peaks. Then check whether any device needs one rail to come up before another, and whether enable and power-good signals enforce that order.

Decoupling comes next. Each supply pin needs the capacitor value and placement the datasheet recommends, and each regulator needs input and output capacitors that suit its stability requirements. Add bulk capacitance where load steps are large, and remember that ceramic capacitors lose effective capacitance as DC bias increases.

Open every datasheet and compare each pin function with what the schematic assumes. A 3.3 V output driving a 1.8 V input can exceed the absolute maximum rating, and 5 V tolerance is a per-pin property, not a family-wide one. Open-drain outputs and buses such as I2C need pull-ups sized for the supply voltage and bus capacitance, and any input that must not float needs a defined state.

Reset, boot-mode and strap pins deserve their own pass because they are sampled at startup and fail in confusing ways. Confirm default states, required pull directions and whether other circuitry shares those pins. For clocks, calculate the crystal load capacitance from the specified load, the two capacitors and an allowance for stray capacitance, then check that the frequency tolerance suits every peripheral that depends on it.

Make sure the board can be programmed and debugged before anything else. Check the SWD or JTAG header pinout, the reference voltage pin and the reset connection against the probe you will actually use. Add test points for every power rail, ground, the main clocks and key communication buses.

Then look at protection. Interfaces that leave the board usually need ESD protection close to the connector, supply inputs may need reverse-polarity protection, and power paths may need a fuse, current limit or similar overcurrent protection. Choose each part for the voltage and signal speed of the line it protects, since some ESD devices add capacitance that suits a slow signal but harms a fast one.

Connector errors are common because pin numbering is viewed from different sides. Verify each pinout against the mating part, confirm pin 1 and the viewing direction, and check that cable-side and board-side connectors are not mirrored. Label power and ground pins clearly so a miswired cable is obvious.

Check ratings with derating in mind. Compare voltage, power dissipation and temperature limits against worst-case conditions and leave margin rather than designing at the limit. Capacitors, resistors, diodes and regulators all have limits that fall with temperature or operating conditions.

Finally, verify every footprint and package against the manufacturer drawing in the datasheet, not against a library name. Check pad pitch, pin 1 position, the pin-to-pad mapping of multi-pin parts and thermal pad requirements. Printing a footprint at full scale and placing the real part on it is a quick sanity check for unusual packages.

A schematic that is hard to read hides errors. Use hierarchical sheets organised by function, consistent and descriptive net names, and clear signal direction between sheets. Avoid unnamed nets for anything important and keep power symbols unambiguous.

Review the bill of materials while the schematic is still open. Check each part for lifecycle status and availability, and confirm that an approved alternate exists for passives and key active parts. Flag single-source components early, because a footprint that cannot accept an alternate limits your options later.

A good review ends with notes that tell the layout engineer what the schematic cannot show. List the nets that need controlled impedance and the target value, plus differential pairs and any length-matching requirements. Mark nets that carry high current so trace width and copper area are chosen on purpose.

Add keep-out and placement notes too: antenna clearance, crystal and sensitive analogue areas, connector positions, mechanical height limits and thermal concerns. Call out decoupling capacitors that must sit close to specific pins. These notes turn the schematic into a specification the layout can be checked against.

Use this list as a sign-off sheet. Each item should be checked against datasheets and initialled before layout starts.

Most schematic mistakes do not announce themselves at the desk. They appear at assembly, at first power-up, during firmware bring-up or, in the worst case, in the field. The table shows typical examples and the stage at which each is usually caught.